Cadence Allegro and OrCAD 17.20.0002016 HF033
Cadence Allegro and OrCAD 17.20.0002016 HF033 | 2.6 Gb
Cadence Design Systems, Inc. has released an update (HF033) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.0002016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
Fixed CCRs: SPB 17.20.0002016 HF033
About Allegro and OrCAD 17.22016. The OrCAD 17.22016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.22016 that address challenges with flex and rigidflex design as well as mixedsignal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
OrCAD Flex and RigidFlex Technologies
To enable a faster and more efficient flex and rigidflex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.22016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stackup by zone for flex and rigidflex designs, Interlayer checks for rigidflex designs, Contour and arcaware routing.
New CrossSection Editor
In the OrCAD PCB Designer 17.22016 release, the CrossSection Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a onestop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The CrossSection Editor has been enhanced to support multiple stackups for rigidflex design, each capable of supporting conductor and nonconductor layers such as Soldermask and Coverlay.
New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.22016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keepouts within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
OrCAD PCB Designer 17.22016 Features
The OrCAD PCB Designer 17.22016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and easeofuse. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, realtime, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a pagebypage basis. The Graphical Design Difference Viewer generates an interactive singlereport HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multilevel abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.22016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located here
About HotFix. A HotFix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, HotFix releases are not periodically scheduled. Simply requesting a HotFix does not automatically guarantee that the customer will receive it: all HotFix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a HotFix may contain fixes related to problems reported earlier by different customers. All the files included in the HotFix will nevertheless be installed.
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.0002016 HF033
Supported Architectures: x64
Website Home Page : www.cadence.com
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.0002016 and above
Size: 2.6 Gb
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